1. Field of the Invention
This invention relates generally to semiconductor processes for forming transistors and, more specifically, to processes for forming local interconnects to a gate of either a planar or nonplanar transistor on a semiconductor substrate.
2. Description of the Related Art
Transistors such as planar transistors have been the core of integrated circuits for several decades. During the use of transistors, the size of the individual transistors has steadily decreased through advances in process development and the need to increase feature density. Current scaling employs 32 nm technologies with development also progressing towards 22 nm and 15 nm technologies.
Development in 15 nm process technology is producing the need for self-aligned contact to gate or self-aligned local interconnect to gate flow in the transistor. A self-aligned process is needed to avoid contact to gate shorts and allow channel length scaling at 15 nm. In addition, other problems may be associated with the fact that the metal layer is likely to be unidirectional SIT (sidewall image transfer). Thus, a means to pull the metal (e.g., metal 1) output port layer on an output away from the transistor cell border may be needed to achieve a manufacturable metal tip to tip spacing to a neighboring cell without a 1 CPP (contact-to-poly-pitch) area penalty.
Currently, there is development in using self-aligned contact to gate flow. This process flow, however, for 15 nm technology may require 2 steps to print a mask for contact to gate separate from 2 steps to print a mask for contact to source/drain due to the resolution constraints of the stepper used to print the patterns used in the masks. The contact to gate process may also require at least one additional metal layer to complete cell routes over current technologies because the metal layer has to be unidirectional.
Currently, there has been little development in the use of selective or self-aligned local interconnects to gate. It is not possible to easily split a local interconnect layer into separate mask sets (as is done for the contact to gate process) because not all local interconnect routes are to be connected to the gate even though some local interconnect routes may pass over the gate. Further, decomposition of the local interconnect pattern is not likely possible without severe design rule restrictions and/or other disadvantages.
Thus, there is a need for a process flow that allows selective local interconnect to be routed over the field and make a connection to the gate or not make a connection to the gate within the transistor cell. The process flow described herein may accomplish manufacturable metal tip to tip spacing to the neighboring cell without the 1 CPP area penalty by allowing routing of the local interconnect back from the output and back over to the gate without connecting to the gate. The local interconnect may then be connected to a via interconnect layer and to a metal (e.g., metal 1) layer while maintaining acceptable metal tip to tip spacing with the neighboring cell. The local interconnect line width may be less than a nominal target for the metal layer so that there may be more tolerance at the same pitch in a double pattern approach or a SIT based approach for local interconnect.
The process flow described herein allows a pattern to define areas where the local interconnect routes over the gate and a connection to the gate is desired as well as define areas where local interconnect routes over the gate and no connection to the gate is desired. This allows the local interconnect to be a routing layer over field and help make connections within the transistor cell. Such routing of the local interconnect may improve the density of the routing layout since the local interconnect spacing to a gate can be zero or less than zero. Without using the process flow described herein, gate tip to local interconnect spacing may have to be at least one full routing pitch or more away from the gate tip to avoid gate to local interconnect shorts or leakage as no routes over gates without making a connection would be allowed.
Using EUV (extreme ultraviolet) instead of current techniques (such as immersion lithography or 193 nm lithography) may allow patterning without the need for pitch splitting or double patterning. Even with the use of EUV lithography, however, pattern decomposition would likely still be needed for routing with self-aligned local contacts. The use of EUV and local interconnect routing with the process flow described herein may, however, eliminate the need for pattern decomposition and/or the use of double patterning or pitch splitting.